 |
The Second International Conference on Advances in System Testing and Validation Lifecycle VALID 2010 August 22-27, 2010 - Nice, France |
| Call for Papers |
Complex distributed systems with heterogeneous interconnections operating at different speeds and based on various nano- and micro-technologies raise serious problems of testing, diagnosing, and debugging. Despite current solutions, virtualization and abstraction for large scale systems provide less visibility for vulnerability discovery and resolution, and make testing tedious, sometimes unsuccessful, if not properly thought from the design phase.
The conference on advances in system testing and validation considers the concepts, methodologies, and solutions dealing with designing robust and available systems. Its target covers aspects related to debugging and defects, vulnerability discovery, diagnosis, and testing.
The inaugural conference VALID 2010 continues a series of events focusing on designing robust components and systems with testability for varia features of behavior and interconnection. The conference will provide a forum where researchers shall be able to present recent research results and new research problems and directions related to them. The conference seeks contributions presenting novel result and future research in all aspects of robust design methodologies, vulnerability discovery and resolution, diagnosis, debugging, and testing.
The topics suggested by the conference can be discussed in term of concepts, state of the art, research, standards, implementations, running experiments, applications, and industrial case studies. Authors are invited to submit complete unpublished papers, which are not under review in any other conference or journal in the following, but not limited to, topic areas. All tracks are open to both research and industry contributions.
Robust design methodologies
Designing methodologies for robust systems
Secure software techniques
Industrial real-time software
Defect avoidance
Cost models for robust systems
Design for testability
Design for reliability and variability
Design for adaptation and resilience
Design for fault-tolerance and fast recovery
Design for manufacturability, yield and reliability
Design for testability in the context of model-driven engineering
Vulnerability discovery and resolution
Vulnerability assessment
On-line error detection
Vulnerabilities in hardware security
Self-calibration
Alternative inspections
Non-intrusive vulnerability discovery methods
Embedded malware detection
Defects and Debugging
Debugging techniques
Component debug
System debug
Software debug
Hardware debug
System debug
Power-ground defects
Full-open defects in interconnecting lines
Physical defects in memories and microprocessors
Zero-defect principles
Diagnosis
Diagnosis techniques
Advances in silicon debug and diagnosis
Error diagnosis
History-based diagnosis
Multiple-defect diagnosis
Optical diagnostics
Testability and diagnosability
Diagnosis and testing in mo bile environments
System and feature testing
Test strategy for systems-in-package
Testing embedded systems
Testing high-speed systems
Testing delay and performance
Testing communication traffic and QoS/SLA metrics
Testing robustness
Software testing
Hardware testing
Supply-chain testing
Memory testing
Microprocessor testing
Mixed-signal production test
Testing multi-voltage domains
Interconnection and compatibility testing
Testing techniques and mechanisms
Fundamentals for digital and analog testing
Emerging testing methodologies
Engineering test coverage
Designing testing suites
Statistical testing
Functional testing
Parametric testing
Defect- and data-driven testing
Automated testing
Embedded testing
Autonomous self-testing
Low cost testing
Optimized testing
Testing systems and devices
Test standards
Testing of wireless communications systems
Testing of mobile wireless communication systems
Testing of wireless sensor networks
Testing of radio-frequency identification systems
Testing of ad-hoc networks
Testing methods for emerging standards
Hardware-based prototyping of wireless communication systems
Physical layer performance verification
On-chip testing of wireless communication systems
Modeling and simulation of wireless channels
Noise characterization and validation
Case studies and industrial applications of test instruments
Software verification and validation
High-speed interface verification and fault-analysis
Software testing theory and practice
Model-based testing
Verification metrics
Service/application specific testing
Model checking
OO software testing
Testing embedded software
Quality assurance
Empirical studies for verification and validation
Software inspection techniques
Software testing tools
New approaches for software reliability verification and validation
Testing and validation of run-time evolving systems
Automated testing for run-time evolving systems
Testing and validation of evolving systems
Testing and validation of self-controlled systems
Testing compile-time versus run-time dependency for evolving systems
On-line validation and testing of evolving at run-time systems
Modeling for testability of evolving at run-time systems
Near real-time and real-time monitoring of run-time evolving systems
Verification and validation of reflective models for testing
Verification and validation of fault tolerance in run-time evolving systems
Feature-oriented testing
Testing user interfaces and user-driven features
Privacy testing
Ontology accuracy testing
Testing semantic matching
Testing certification processes
Testing authentication mechanisms
Testing biometrics methodologies and mechanisms
Testing cross-nation systems
Testing system interoperability
Testing system safety
Testing system robustness
Testing temporal constraints
Testing transaction-based properties
Directed energy test capabilities /microwave, laser, etc./
Testing delay and latency metrics;
Domain-oriented testing
Testing autonomic and autonomous systems
Testing intrusion prevention systems
Firewall testing
Information assurance testing
Testing social network systems
Testing recommender systems
Testing biometric systems
Testing diagnostic systems
Testing on-line systems
Testing financial systems
Testing life threatening systems
Testing emergency systems
Testing sensor-based systems
Testing testing systems;
INSTRUCTION FOR THE AUTHORS
Authors of selected papers will be invited to submit extended versions to one of the IARIA Journals.
Publisher: CPS (see: http://www2.computer.org/portal/web/cscps/)
Archived: IEEE CSDL (Computer Science Digital Library) and IEEE Xplore
Submitted for indexing: Elsevier's EI Compendex Database, EI’s Engineering Information Index
Other indexes are being considered: INSPEC, DBLP, Thomson Reuters Conference Proceedings Citation Index
Important deadlines:
Considering Easter Holidays, deadline is April 5, 2010| Submission (full paper) | |
| Notification | May 2 , 2010 |
| Registration | May 15, 2010 |
| Camera ready | May 22, 2010 |
Only .pdf or .doc files will be accepted for paper submission. All received papers will be acknowledged via an automated system.
Final author manuscripts will be 8.5" x 11", not exceeding 6 pages; max 4 extra pages allowed at additional cost. The formatting instructions can be found on the Instructions page. Helpful information for paper formatting can be found on the here.
Your paper should also comply with the additional editorial rules.
Once you receive the notification of paper acceptance, you will be provided by the publisher an online author kit with all the steps an author needs to follow to submit the final version. The author kits URL will be included in the letter of acceptance.
Posters
Posters are welcome. Please submit the contributions following the instructions for the regular submissions using the "Submit a Paper" button and selecting the contribution type as poster. Submissions are expected to be 6-8 slide deck. Posters will not be published in the Proceedings. One poster with all the slides together should be used for discussions. Presenters will be allocated a space where they can display the slides and discuss in an informal manner. The poster slide decks will be posted on the IARIA site.
For more details, see the Posters explanation page.
Work in Progress
Work-in-progress contributions are welcome. Please submit the contributions following the instructions for the regular submissions using the "Submit a Paper" button and selecting the contribution type as work in progress. Authors should submit a four-page (maximum) text manuscript in IEEE double-column format including the authors' names, affiliations, email contacts. Contributors must follow the conference deadlines, describing early research and novel skeleton ideas in the areas of the conference topics. The work will be published in the conference proceedings.
For more details, see the Work in Progress explanation page
Technical marketing/business/positioning presentations
The conference initiates a series of business, technical marketing, and positioning presentations on the same topics. Speakers must submit a 10-12 slide deck presentations with substantial notes accompanying the slides, in the .ppt format (.pdf-ed). The slide deck will not be published in the conference’s CD Proceedings. Presentations' slide decks will be posted on the IARIA's site. Please send your presentations to petre@iaria.org.
Tutorials
Tutorials provide overviews of current high interest topics. Proposals should be for three hour tutorials. Proposals must contain the title, the summary of the content, and the biography of the presenter(s). The tutorials' slide decks will be posted on the IARIA's site. Please send your proposals to petre@iaria.org
Panel proposals:
The organizers encourage scientists and industry leaders to organize dedicated panels dealing with controversial and challenging topics and paradigms. Panel moderators are asked to identify their guests and manage that their appropriate talk supports timely reach our deadlines. Moderators must specifically submit an official proposal, indicating their background, panelist names, their affiliation, the topic of the panel, as well as short biographies. The panel's slide deck will be posted on the IARIA's site.
For more information, petre@iaria.org
Workshop proposals
We welcome workshop proposals on issues complementary to the topics of this conference. Your requests should be forwarded to petre@iaria.org.
